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SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
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SpaceWire Endpoint implementation
Hráček, Marek ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This work deals with the SpaceWire standard, that is used to convey the communication between modules and subsystems on board spacecrafts. Theoretical part describes standard, the way it operates and logic layers in which various functions are divided. Next part is describing design of SpaceWire endpoint itself. Presented are individual components and solutions to implement features of standard. Last chapter deals with device utilization and reached speed after synthesis with specific FPGA.
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SW/HW toolset for board-level tests
Ostřížek, Tomáš ; Pavlík, Michal (referee) ; Bohrn, Marek (advisor)
This thesis describes the design of a board-level testing platform for monitoring and driving a selected set of interfaces used in space applications. The requirements of these devices are based on the corresponding ECSS, IEEE, and TIA standards described in the theoretical part of this thesis. The designed testing device is controlled by the Xilinx Zynq-7000 system-on-chip and is connected to a control PC via an Ethernet connection. The hardware, designed on a schematic level is responsible for meeting the standards' requirements. The software part consists of a Python module for the control PC providing a set of functions to be used in the testing process and a C application for the embedded ARM processor that forwards the data through the AXI interface to the interface drivers in the programmable logic.
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FPGA Implementation of RMAP Initiator and Target
Walletzký, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.
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Remote Memory Access Protocol Controller For Spacewire Network
Walletzký, Ondřej
This article describes design and implementation of Remote Memory Access Protocol controller, namely the initiator module specified in the ECSS-E-ST-50-52C standard. It provides general description of its architecture and describes some of its subcomponents. Finally, it summarizes resource utilization and maximum theoretical clock frequency for different configurations when synthesized for Spartan-3 FPGA chip.
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SW/HW toolset for board-level tests
Ostřížek, Tomáš ; Pavlík, Michal (referee) ; Bohrn, Marek (advisor)
This thesis describes the design of a board-level testing platform for monitoring and driving a selected set of interfaces used in space applications. The requirements of these devices are based on the corresponding ECSS, IEEE, and TIA standards described in the theoretical part of this thesis. The designed testing device is controlled by the Xilinx Zynq-7000 system-on-chip and is connected to a control PC via an Ethernet connection. The hardware, designed on a schematic level is responsible for meeting the standards' requirements. The software part consists of a Python module for the control PC providing a set of functions to be used in the testing process and a C application for the embedded ARM processor that forwards the data through the AXI interface to the interface drivers in the programmable logic.
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|
|
FPGA Implementation of RMAP Initiator and Target
Walletzký, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.
|
|
|
SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
|
|
|
SpaceWire Endpoint implementation
Hráček, Marek ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This work deals with the SpaceWire standard, that is used to convey the communication between modules and subsystems on board spacecrafts. Theoretical part describes standard, the way it operates and logic layers in which various functions are divided. Next part is describing design of SpaceWire endpoint itself. Presented are individual components and solutions to implement features of standard. Last chapter deals with device utilization and reached speed after synthesis with specific FPGA.
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